1. Field of the Invention
The present invention relates to a method for growing Group III nitride semiconductor crystal on a concave-convex substrate and a Group III nitride semiconductor.
2. Background Art
When a Group III nitride semiconductor light-emitting device is produced by crystal growth of Group III nitride semiconductor on a sapphire substrate, a technique has been developed to form concaves and convexes on a Group III nitride semiconductor growing surface of the sapphire substrate to improve the light extraction performance (e.g. Japanese Patent Application Laid-Open (kokai) Nos. 2004-200523 and 2005-101566).
Japanese Patent Application Laid-Open (kokai) No. 2003-526907 discloses that concaves and convexes are formed in the form of stripes on a sapphire substrate, GaN is vertically grown on the top surfaces of the posts, and further laterally grown, thereby obtaining a GaN semiconductor having a low threading dislocation density.
However, when Group III nitride semiconductor is grown on the concave-convex sapphire substrate by these methods, voids are formed near the side surfaces of the trenches or posts, resulting in a problem that crystallinity and flatness of Group III nitride semiconductor are deteriorated.
Therefore, Japanese Patent Application Laid-Open (kokai) No. 2003-318441 discloses that sides in planar view of trenches or posts intersect with an a-plane of a sapphire substrate. When the trenches or posts are formed in such a manner, GaN is grown on the top surfaces of the posts of the sapphire substrate and the bottom surfaces of the trenches, and GaN is difficult to grow on side surfaces of the trenches or posts. As the growth progresses, the crystals are combined together, thereby obtaining GaN having superior crystallinity and high flatness, with no void formed therein. On the other hand, when sides in planar view of trenches or posts are parallel to an a-plane of a sapphire substrate, lateral growth of the GaN grown on the trenches or posts is slow. Therefore, the vicinity of the side surfaces of the trenches or posts is difficult to be filled with GaN, and the surface flatness of GaN is deteriorated.
Japanese Patent Application Laid-Open (kokai) No. 2011-77265 discloses that all side surfaces of posts on a substrate having an a-plane or c-plane main surface are the surfaces which inhibit the crystal growth of Group III nitride semiconductor. It is also disclosed that when the posts are hexagonal prisms, the angle between each side of hexagons in planar view and the m-axis is 15°.
When the posts or trenches are formed in a unidirectional stripe pattern, light propagated along this stripe direction fail to be scattered, resulting in insufficient improvement of external quantum efficiency. Japanese Patent Application Laid-Open (kokai) No. 2012-114204 discloses that a first stripe structure is formed in a first axis direction, and the first stripe structure is etched in a second axis direction crossing the first axis direction so that the second stripe structure is overlapped on the first stripe structure, thereby four differences in level are provided. Thus, the light propagated in parallel to the first stripe structure is scattered by the second stripe structure, resulting in the improvement of external quantum efficiency.
However, as in Japanese Patent Application Laid-Open (kokai) No. 2012-114204, when a Group III nitride semiconductor is grown on a surface having posts or trenches arranged in a grid pattern, Group III nitride semiconductor is grown in a complicated growth mode because crystal orientation is different between the side surface of the first stripe structure and the side surface of the second stripe structure. Therefore, there is a problem that threading dislocations are locally distributed, resulting in the reduction of the internal quantum efficiency and the yield ratio of production.